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Freescale Semiconductor Advance Information
Document Number: MC33982 Rev. 12.0, 1/2007
Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 m)
The 33982B is a self-protected silicon 2.0 m high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982B is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982B is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. Features
33982B
HIGH-SIDE SWITCH
Bottom View PNA SUFFIX SCALE 1:1 98ARL10521D 16-PIN PQFN
* Single 2.0 m Max High-Side Switch with Parallel Input or SPI Control ORDERING INFORMATION * 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 A Temperature Device Package * Output Current Monitoring with Two SPI-Selectable Current Range (TA) Ratios MC33982BPNA/R2 -40C to 125C 16 PQFN * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Time-out, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature Shutdown, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status * Enhanced -16 V Reverse Polarity VPWR Protection
VDD VDD VDD VPWR
33982B
VDD I/O I/O SO SCLK FS WAKE SI SCLK CS SO RST IN LOAD A/D CSNS FSI GND HS VPWR GND
MCU
CS SI I/O I/O
GND
PWR GND
Figure 1. 33982B Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC IUP
Internal Regulator Programmable Switch Delay 0 ms-525 ms
Overvoltage Protection Selectable Slew Rate Gate Drive HS Selectable Overcurrent High Detection 150 A or 100 A Selectable Overcurrent Low Detection Blanking Time 0.15 ms-155 ms Selectable Overcurrent Low Detection 15 A-50 A Open Load Detection
CS SO SPI 3.0 MHz SI SCLK FS IN RST WAKE
Logic
IDWN
RDWN
Overtemperature Detection
VIC IUP
Programmable Watchdog 310 ms-2500 ms FSI
Selectable Output Current Recopy 1/5400 or 1/40000
GND
Figure 2. 33982B Simplified Internal Block Diagram
CSNS
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
WAKE
CSNS
SCLK
VDD
RST
FSI
12 11 10 9
NC
Figure 3. 33982B Pin Connections Table 1. Pin Definitions Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 15.
Pin Number 1 Pin Name CSNS Pin Function Output Formal Name Output Current Monitoring Definition This pin is used to output a current proportional to the high-side output current and used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. This pin is used to input a Logic [1] signal in order to enable the watchdog timer function. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The Input pin is used to directly control the output. This is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. The value of the resistance connected between this pin and ground determines the state of the output after a watchdog time-out occurs. This input pin is connected to a chip select output of a master microcontroller (MCU). This input pin is connected to the MCU providing the required bit shift clock for SPI communication. This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device in a daisy chain of devices. This is an external voltage input pin used to supply power to the SPI circuit.
SO
CS
FS
IN
15 HS
SI
87
65
4
32
1
13 GND TRANSPARENT TOP VIEW 14 VPWR
16 HS
2
WAKE
Input
Wake
3
RST
Input
Reset (Active Low)
4 5
IN FS
Input Output
Direct Input Fault Status (Active Low) Fail-Safe Input
6
FSI
Input
7
CS
Input
Chip Select (Active Low) Serial Clock
8
SCLK
Input
9
SI
Input
Serial Input
10
VDD
Input
Digital Drain Voltage (Power)
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PIN CONNECTIONS
Table 1. Pin Definitions (continued) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 15.
Pin Number 11 Pin Name SO Pin Function Output Formal Name Serial Output Definition This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain of devices. This pin may not be connected. This pin is the ground for the logic and analog circuitry of the device. This pin connects to the positive power supply and is the source input of operational power for the device. Protected high-side power output to the load. Output pins must be connected in parallel for operation.
12 13 14
NC GND VPWR
NC Ground Input
No Connect Ground Positive Power Supply High-Side Output
15, 16
HS
Output
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating ELECTRICAL RATINGS Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage
(1)
Symbol
Value
Unit
VPWR -16 to 41 VDD VIN, RST, FSI, CSNS, SI, SCLK, CS, FS VSO ICL(WAKE) ICL(CSNS) IHS VHS 41 -15 -0.3 to 5.5 - 0.3 to 7.0
V
V V
SO Output Voltage (1) WAKE Input Clamp Current CSNS Input Clamp Current Output Current Output Voltage Positive Negative Output Clamp Energy ESD Voltage
(4) (3) (2)
- 0.3 to VDD + 0.3 2.5 10 60
V mA mA A V
ECL
1.5
J V
Human Body Model (HBM) Charge Device Model (CDM) Corner Pins (1, 12, 15, 16) All Other Pins (2, 11, 13, 14)
VESD1 VESD3
2000 750 500
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance Junction-to-Case Junction-to-Ambient Peak Package Reflow Temperature During Reflow
(6), (7) (5)
Symbol
Value
Unit
C
TA TJ TSTG - 40 to 125 - 40 to 150 - 55 to 150
C C/W
RJC RJA TPPRT
<1.0 20 Note 7 C
Notes 1. Exceeding this voltage limit may cause permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150C). 4. 5. 6. 7. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ); ESD3 testing is performed in accordance with the Charge Device Model (CDM), Robotic (Czap = 4.0 pF). Device mounted on a 2s2p test board per JEDEC JESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT Battery Supply Voltage Range Full Operational VPWR Operating Supply Current Output ON, IHS = 0 A VPWR Supply Current Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25C TJ = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Output Shutdown Threshold Undervoltage Hysteresis
(9) (8)
Symbol
Min
Typ
Max
Unit
VPWR 6.0 IPWR(ON) - IPWR(SBY) - IPWR(SLEEP) - - VDD(ON) IDD(ON) - - IDD(SLEEP) VPWR(OV) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) - 28 0.2 5.0 - - - - - 32 0.8 5.5 0.25 - 1.0 5.0 5.0 36 1.5 6.0 - 5.0 4.5 - - 5.0 10 50 5.5 - 5.0 - 20 - 27
V
mA
mA
A
V mA
A V V V V V
Undervoltage Power-ON Reset POWER OUTPUT Output Drain-to-Source ON Resistance (IHS = 30 A, TJ = 25C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS = 30 A, TJ = 150C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance (IHS = 30 A, TJ = 25C) VPWR = -12 V
(10)
RDS(ON) - - - RDS(ON) - - - RDS(ON) - 2.0 4.0 - - - 5.1 3.4 3.4 - - - 3.0 2.0 2.0
m
m
m
Notes 8. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 9. 10. This applies when the undervoltage fault is not latched (IN = 0). Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT (CONTINUED) Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A Current Sense Ratio (CSR1) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A Current Sense Clamp Voltage CSNS Open, IHS = 59.0 A Open Load Detection Current (11) Output Fault Detection Threshold Output Programmed OFF IOLDC VOLD(THRES) 2.0 3.0 4.0 VCL(CSNS) 4.5 30 6.0 - 7.0 100 A V - 25 -19 -18 -17 -18 -18 - - - - - - 25 19 18 17 18 18 V CSR1_ACC - 20 -14 -13 -12 -13 -13 - - - - - - 20 14 13 12 13 13 % CSR0 CSR1 CSR0_ACC - - 1/5400 1/40000 - - % IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 41 36 32 29 25 20 16 12 50 45 40 35 30 25 20 15 59 54 48 41 35 30 24 18 - IOCH0 IOCH1 120 80 150 100 180 120 A A Symbol Min Typ Max Unit
Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT (CONTINUED) Output Negative Clamp Voltage 0.5 A < IHS < 2.0 A, Output OFF Overtemperature Shutdown (12) Overtemperature Shutdown Hysteresis (12) CONTROL INTERFACE Input Logic High Voltage (13) Input Logic Low Voltage (13) Input Logic Voltage Hysteresis (14) Input Logic Pulldown Current (SCLK, IN, SI) RST Input Voltage Range SO, FS Tri-State Capacitance (15) Input Logic Pulldown Resistor (RST) and WAKE Input Capacitance (15) WAKE Input Clamp Voltage (16) ICL(WAKE) < 2.5 mA WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA FS, SO Low-State Output Voltage IOL = -1.6 mA SO Tri-State Leakage Current CS > 0.7 VDD Input Logic Pullup Current (17) CS, VIN > 0.7 VDD FSI Input Pin External Pulldown Resistance FSI Disabled, HS Indeterminate FSI Enabled, HS OFF FSI Enabled, HS ON RFS RFSdis RFSoff RFSon - 6.0 30 0.0 10 - 1.0 14 - IUP 5.0 - 20 k ISO(LEAK) -5.0 0.0 5.0 A VSOL - 0.2 0.4 A VSOH 0.8 VDD - - V VF(WAKE) - 2.0 - -0.3 V VIH VIL VIN(HYS) IDWN VRST CSO RDWN CIN VCL(WAKE) 7.0 - 14 V 0.7 VDD - 100 5.0 4.5 - 100 - - - 600 - 5.0 - 200 4.0 - 0.2 VDD 1200 20 5.5 20 400 12 V V mV A V pF k pF V TSD TSD(HYS) VCL - 20 160 5.0 - 175 - -15 190 20 V Symbol Min Typ Max Unit
C C
Notes 12. Guaranteed by process monitoring. Not production tested. 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. 15. 16. 17. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING Output Rising Slow Slew Rate A (DICR D3 = 0) (18) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (18) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate B (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (18) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (18) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Turn-ON Delay Time in Fast/Slow Slew Rate (20) DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (21) DICR = 1 Direct Input Switching Frequency (DICR D3 = 0) f PWM
(21)
Symbol
Min
Typ
Max
Unit
SRRA_SLOW 0.2 SRRB_SLOW 0.03 SRRA_FAST 0.4 SRRB_FAST 0.03 SRFA_SLOW 0.2 SRFB_SLOW 0.03 SRFA_FAST 0.8 SRFB_FAST 0.1 0.35 1.2 2.0 4.0 0.1 0.3 0.6 1.2 0.1 1.2 1.0 4.0 0.1 0.3 0.6 1.2
V/s
V/s
V/s
V/s
V/s
V/s
V/s
V/s
tDLY(ON)
1.0 18 100
s
tDLY_SLOW(OFF)
20 230 500
s
tDLY_FAST(OFF)
10 - 60 300 200 -
s
Hz
Notes 18. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V. These parameters are guaranteed by process monitoring. 19. Rise and Fall Slow Slew Rates B measured across a 5.0 resistive load at high-side output = VPWR - 3.5 V to VPWR - 0.5 V. These parameters are guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VHS = 0.5 V with RL = 5.0 resistive load. 21. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VHS = VPWR - 0.5 V with RL = 5.0 resistive load.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING (CONTINUED) Overcurrent Low Detection Blanking Time (OCLT [1:0]) 00 01 10 11 Overcurrent High Detection Blanking Time CS to CSNS Valid Time
(22)
Symbol
Min
Typ
Max
Unit
ms
t OCL0 t OCL1 t OCL2 t OCL3 t OCH t CNSVAL t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7
(23)
108 7.0 0.8 0.08 1.0 -
155 10 1.2 0.15 10 -
202 13 1.6 0.25 20 10 s s ms
Output Switching Delay Time (OSD [2:0]) 000 001 010 011 100 101 110 111 Watchdog Time-out (WD [1:0]) 00 01 10 11 SPI INTERFACE CHARACTERISTICS Recommended Frequency of SPI Operation Required Low State Duration for RST (24) - 52 105 157 210 262 315 367 0.0 75 150 225 300 375 450 525 - 95 195 293 390 488 585 683
ms
t WDTO0 t WDTO1 t WDTO2 t WDTO3
434 207 1750 875
620 310 2500 1250
806 403 3250 1625
f SPI t WRST
- -
- 50
3.0 167
MHz ns
Notes 22. Time necessary for the CSNS to be within 5% of the targeted value. 23. Watchdog time-out delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 24. RST low duration measured with outputs enabled and going to OFF or disabled condition.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TA 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI INTERFACE CHARACTERISTICS Rising Edge of CS to Falling Edge of CS (Required Setup Time) (25) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (25) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Required High State Duration of SCLK (Required Setup Time) (25) Required Low State Duration of SCLK (Required Setup Time)
(25) (25) (25)
Symbol
Min
Typ
Max
Unit
t CS t ENBL t LEAD t WSCLKH t WSCLKL t LAG t SI(SU) t SI(HOLD) t RSO
- - - - - - - -
- - 50 - - 50 25 25
300 5.0 167 167 167 167 83 83
ns s ns ns ns ns ns ns ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) (26) Falling Edge of SCLK to SI (Required Setup Time) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (26) SI, CS, SCLK, Incoming Signal Fall Time
(26) (26)
-
25
50 ns
t FSO
- 25 - - - 65 50 50 50 145 145
t RSI t FSI t SO(EN) t SO(DIS) t VALID
- - - -
ns ns ns ns ns
Time from Falling Edge of CS to SO Low Impedance (27) Time from Rising Edge of CS to SO High Impedance Time from Rising Edge of SCLK to SO Data Valid (29) 0.2 VDD SO 0.8 VDD, CL = 200 pF Notes 25. 26. 27. 28. 29.
(28)
-
65
105
Maximum setup time required for the 33982B is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pullup on CS. Time required for output status data to be terminated at SO. 1.0 k on pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR VPWR VPWR - 0.5V
VPWR --3.5 3V V
VPWR -0.5 V V PWR
SRRB_SLOW & SRRB_FAST SRrB
SRFB_SLOW & SRFB_FAST SRfB
SRfA SRFA_SLOW & SRFA_FAST SRRA_SLOW & SRRA _FAST SRrA
0.5V 0.5
V t DLY_SLOW(OFF) & tDLY_FAST(OFF) Tdly(off)
HS
t DLY(ON) Tdly(on)
Figure 4. Output Slew Rate and Time Delays
IOCHx Load Current IOCLx t OCH Time t OCLx Figure 5. Overcurrent Shutdown
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
t OCHx t OCL3 t OCL2 t OCL1 t OCL0
Figure 6. Overcurrent Low and High Detection
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ELECTRICAL CHARACTERISTICS
Figure 6 illustrates the overcurrent detection level
(IOCLX, IOCHX) the device can reach for each overcurrent detection blanking time (tOCHX, tOCLX):
* During tOCHX, the device can reach up to Ioch0 overcurrent level. * During tOCL3 or tOCL2 or tOCL1 or tOCL0, the device can be programmed to detect up to Iocl0.
VIH V
IH
RSTB RST
0.2 VDD 0.2 VDD
TwRSTB
VIL TCSB t CS
VIL
t WRST
t ENBL
TENBL
0.7 VDD 0.7VDD CS CSB 0.2 VDD 0.7VDD tTlead LEAD t WSCLKh TwSCLKh t RSI
TrSI
VIH V
IH
VIL V
IL
t LAG Tlag
VIH VIH VIL V
SCLK SCLK
0.7 VDD 0.7VDD 0.2 VDD
0.2VDD
tTSIsu SI(SU)
IL
t WSCLKl TwSCLKl
t SI(HOLD) TSI(hold)
tTfSI FSI
VIH V
IH
SI SI
Don't Care
0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD
Valid
Don't Care
Valid
Don't Care
VIH VIL
Figure 7. Input Timing Switching Characteristics
t RSI
tFSI
TrSI
3.5 3.5V V
TfSI VOH VOH 50% 1.0V 1.0 V VOL VOL
SCLK SCLK
t SO(EN)
TdlyLH
SO SO
0.7 VDD VDD
VOH VOH VOL VOL
0.2 VDD 0.2 VDD TrSO t RSO TVALID t VALID
Low-to-High Low to High
SO
SO
0.7 VDD High to Low High-to-Low 0.7 VDD
TfSO t FSO
VOH VOH
TdlyHL
t SO(DIS)
0.2VDD 0.2 VDD
VOL VOL
Figure 8. SCLK Waveform and Valid SO Data Delay Time
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33982B is a self-protected silicon 2.0 m high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982B is designed for harsh environments, including selfrecovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982B is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
The CSNS pin outputs a current proportional to the highside output current and used externally to generate a groundreferenced voltage for the microcontroller to monitor output current.
operation are disabled. This pin incorporates an active internal pullup current source.
CHIP SELECT (CS)
This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled up logic HIGH disregard the SPI communication data sent. This pin incorporates an active internal pullup current source.
WAKE (WAKE)
This pin is used to input a Logic [1] signal in order to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown.
RESET (RST)
This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The pin also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This pin should not be allowed to be logic HIGH until VDD is in regulation. This pin has a passive internal pulldown.
SERIAL CLOCK (SCLK)
This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pulldown current source.
DIRECT IN (IN)
The Input pin is used to directly control the output. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI.
SERIAL INTERFACE (SI)
This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device in a daisy chain of devices. The input requires CMOS logic level signals and incorporates an active internal pulldown current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.
FAULT STATUS (FS)
This is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin.
FAIL-SAFE INPUT (FSI)
The value of the resistance connected between this pin and ground determines the state of the output after a watchdog time-out occurs. Depending on the resistance value, either the output is OFF or ON. When the FSI pin is connected to GND, the watchdog circuit and fail-safe
DIGITAL DRAIN VOLTAGE POWER (VDD)
This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
SERIAL OUTPUT (SO)
This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain of devices. This output will remain tri-stated (high impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only active when the CS pin of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package.
HIGH-SIDE OUTPUT (HS)
This pin protects high-side power output to the load. Output pins must be connected in parallel for operation.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33982B has four operating modes: Sleep, Normal, Fault, and Fail-Safe. Table 5 summarizes details contained in succeeding paragraphs. Table 5. Fail-Safe Operation and Transitions to Other 33982B Modes
Mode FS WAKE RST WDTO Comments
Sleep
x
0
0
x
Device is in Sleep mode. All outputs are OFF. Normal mode. Watchdog is active if enabled. The device is currently in Fault mode. The faulted output is OFF. Watchdog has timed out and the device is in FailSafe mode. The output is as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to Logic [0] simultaneously to bring the device out of the Fail-Safe mode or momentarily tied the FSI pin to ground.
Normal
1
x
1
No
Fault
0 0 1 1 1
1 x 0 1 0 1
x 1 1 1 1 0
No
transitions from Logic [0] to Logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current. The watchdog time-out is a multiple of an internal oscillator and is specified in Table 14. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog time-out period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog time-out occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the output will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, OCLT). The watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value for this one) are fully operational. Table 6. Output State During Fail-Safe Mode
RFS (k) High-Side State
FailSafe
1
Yes
0 10 30
Fail-Safe Mode Disabled HS OFF HS ON
x = Don't care.
SLEEP MODE
The default mode of the 33982B is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both Logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to Logic [0]. The device will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 5.
The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is Logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0]. Table 5 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The output can still be driven by the direct input IN. The 33982B uses the battery input to power the output MOSFET-related current sense circuitry and any other internal Logic, providing failsafe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values. Current recopy is active with the default current recopy value.
NORMAL MODE
The 33982B is in Normal mode when: * VPWR is within the normal voltage range. * RST pin is Logic [1]. * No fault has occurred.
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog time-out detection is active when either the WAKE or RST input pin
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES
FAULT MODE
The 33982B indicates the following faults as they occur by driving the FS pin to Logic [0]: * Overtemperature fault * Overvoltage and undervoltage fault * Open load fault * Overcurrent fault (high and low)
The FS pin will automatically return to Logic [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 16).
PROTECTION AND DIAGNOSIS FEATURES
OVERTEMPERATURE FAULT (NON-LATCHING)
The 33982B incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device.
to re-enable the state of output and release FS. The UVF bit will remain set to 1 until the next read operation. The undervoltage protection can be disabled through SPI (bit UV_dis = 1). In this case, the FS and UVF bit do not report any undervoltage fault condition and the output state will not be changed as long as the battery voltage does not drop any lower than 2.5 V.
OPEN LOAD FAULT (NON-LATCHING)
The 33982B incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled through SPI (bit OL_dis). It is recommended to disable the open load
OVERVOLTAGE FAULT (NON-LATCHING)
The 33982B shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled through SPI (bit OV_dis).
detection circuitry (OL_dis bit sets to logic [1]) in case of a permanent open load fault condition.
OVERCURRENT FAULT (LATCHING)
The 33982B has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 6. The eight different overcurrent low detection levels (IOCL0 : IOCL7) are likewise illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCL driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING)
The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to Logic [0], and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers: * If output(s) command is (are) low, FS will go to Logic [1] but the UVF bit will remain set to 1 until the next read operation. * If the output command is ON, then FS will remain at Logic [0]. The output must be turned OFF and ON again
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES
Table 7. Device Behavior in Case of Undervoltage
UV Enable UV Enable UV Enable UV Enable IN=0 IN=0 IN=1 IN=1 (Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR) UV Disable IN=X (Falling or Rising VPWR)
SPSS (VPWR Batter Voltage)
State
VPWR > VPWRUV
Output State FS State SPI Fault Register UVF Bit
OFF 1 0 OFF 0 1 OFF 1
OFF 1 1 until next read OFF 0 1 until next read OFF 1
ON 1 0 OFF 0 1 OFF 1
OFF 0 1 OFF 0 1 OFF 1
OFF 1 0 OFF 1 0 OFF 1 0 OFF 1 0
VPWRUV > VPWR > UVPOR Output State FS State SPI Fault Register UVF Bit UVPOR > VPWR > 2.5 V Output State FS State
SPI Fault Register UVF Bit 1 until next read 1 until next read 1 until next read 1 until next read 2.5 V > VPWR > 0V Output State FS State OFF 1 OFF 1 OFF 1 OFF 1
SPI Fault Register UVF Bit 1 until next read 1 until next read 1 until next read 1 until next read Comments
Typical value; not guaranteed While VDD remains within specified range.
UV fault is not latched
UV fault is not latched
UV fault is latched
REVERSE BATTERY
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gate is enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required.
GROUND DISCONNECT PROTECTION
In the event the 33982B ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the state of the output at the time of disconnection. A 10 k resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exceed its maximum ratings.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire synchronous data transfer with four I /O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI / SO pins of the 33982B follow a first-in first-out (D7 / D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions:
stream of serial data is required on the SI pin, starting with D7 to D0. The internal registers of the 33982B are configured and controlled using a 4-bit addressing scheme, as shown in Table 8. Register addressing and configuration are described in Table 9. The SI input has an active internal pulldown, IDWN.
SERIAL OUTPUT (SO)
The SO pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a Logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 15.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the 33982B device. The serial input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic LOW state whenever CS makes any transition. For this reason, it is recommended that the SCLK pin be in a Logic [0] state whenever the device is not accessed (CS Logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is Logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). (See Figure 9 and Figure 10.)
CHIP SELECT (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a Logic [0] state, the device is capable of transferring information to and receiving information from the MCU. The 33982B latches in data from the input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is Logic [0]. CS should transition from a Logic [1] to a Logic [0] state only when SCLK is a Logic [0]. CS has an active internal pullup, IUP.
SERIAL INTERFACE (SI)
This is a serial interface (SI) command data input pin. SI instruction is read on the falling edge of SCLK. An 8-bit
CSB CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Notes 1. RSTB a Logic [1] state during the above operation. RST NOTES: 1. RST is is in a logic 1 state during the above operation. 2. D7:D0 relate to the most recent most recent ordereddata into the device. 2. D0, D1, D2, ..., and D7 relate to the ordered entry of entry of data into the SPSS 3. OD7:OD0 relate..., and OD7 relate to the first 8 bits of ordered fault and status of the device. 3. OD0, OD1, OD2, to the first 8 bits of ordered fault and status data out data out of the device.
Figure 9. Single 8-Bit Word SPI Communication
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CSB CS
SCLK SCLK
S SI
I
D7
D6
D5
D2
D1
D0
D 7*
D6*
D 5*
D 2*
D 1*
D0*
SO SO
OD7
OD6
OD5
OD2
OD1
OD0
D7
D6
D5
D2
D1
D0
2. D 0 D 1 , D [1] . , a n d D 7 r e l t e th e m s t re c e n t o Notes 1. RST is a, Logic 2 , . .state duringa thet oabove ooperation. r d e r e d e n t r y o f d a t a i n t o t h e S P S S 3. O D 0 , O D 1 , O D 2 , . . ., a n d O D 7 r e la t e t o t h e fir s t 8 b it s o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic e . 4. O D0, O 1 O D 2 , . . . , recent 7 r e p r e s n t t h f i data i t s o o r d e r e d f a u 2. D7:D0 relate Dto ,the most a n d O D orderedeentrye ofr s t 8 b into fthe device. l t a n d s t a t u s d a t a o u t o f t h e S P S S 3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device. 4. OD7:OD0 relate to the firstI 8 bits E 4 b . M U faultPand statusWdata outSof the O M M U N I C A T I O N F G U R of ordered L T I L E 8 b i t ORD P I C device.
NOTES:
1.
R S TT B RS
is in a lo g ic 1 s t a t e d u r in g t h e a b o v e o p e r a t io n .
Figure 10. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit messages. A message is transmitted by the MCU starting with the MSB, D7, and ending with the LSB, D0 (Table 8). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB (D7) is the watchdog bit and in some cases a register address bit; the next three bits, D6 : D4, are used to select the command register; and the remaining four bits, D3 : D0, are used to configure and control the output and its protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data as long as the messages are all multiples of eight bits. Any attempt made to latch in a message that is not eight bits will be ignored. The 33982B has defined registers, which are used to configure the device and to control the state of the output.
Table 9, summarizes the SI registers. The registers are addressed via D6 : D4 of the incoming SPI word (Table 8). Table 8. SI Message Bit Assignment
Bit Sig SI Msg Bit Message Bit Description
MSB
D7
Watchdog in: toggled to satisfy watchdog requirements; also used as a register address bit. Register address bits. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
D6 : D4 D3 : D1
LSB
D0
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 9. Serial Input Address and Configuration Bit Map
SI Register Serial Input Data
set the overcurrent high detection level to one of two levels as defined in Table 11. Table 10. Overcurrent Low Detection Levels
D7 D6 D5 D4 x x x x x 0 1 0 1 x 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1
D3 0 0 SOCH
D2 SOA2 0 SOCL2
D1 SOA1 CSNS EN SOCL1 OCLT1 IN dis OSD1 WD1 0 UV_dis
D0 SOA0 IN_SPI SOCL0
STATR OCR SOCHLR CDTOLR DICR OSDR WDR NAR UOVR TEST
SOCL2 (D2)
SOCL1 (D1)
SOCL0 (D0)
Overcurrent Low Detection (Amperes)
0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
50 45 40 35 30 25 20 15
OL_dis CD_dis FAST SR 0 0 0 0 CSNS high OSD2 0 0 0
OCLT0 0 A/O 1 OSD0 WD0 0 OV_dis 1 1 1
Freescale Internal Use (Test)
Table 11. Overcurrent High Detection Levels
SOCH (D3) Overcurrent High Detection (Amperes)
x = Don't care.
DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation. Address x000 -- Status Register (STATR) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D2, D1, and D0 determine the content of the first eight bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 24.) Address x001 -- Output Control Register (OCR) The OCR register allows the MCU to control the output through the SPI. Incoming message bit D0 (IN_SPI) reflects the desired states of the high-side output: a Logic [1] enables the output switch and a Logic [0] turns it OFF. A Logic [1] on message bit D1 enables the Current Sense (CSNS) pin. Bits D2 and D3 must be Logic [0]. Bit D7 is used to feed the watchdog if enabled. Address x010 -- Select Overcurrent High and Low Register (SOCHLR) The SOCHLR register allows the MCU to configure the output overcurrent low and high detection levels, respectively. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements to match system characteristics. Bits D2 : D0 are used to set the overcurrent low detection level to one of eight possible levels as defined in Table 10. Bit D3 is used to
0 1
150 100
Address x011 -- Current Detection Time and Open Load Register (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before output latches OFF occurs. Bits D1 and D0 allow the MCU to select one of four fault blanking times defined in Table 12. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s. Table 12. Overcurrent Low Detection Blanking Time
OCLT [1:0] Timing
00 01 10 11
155 ms 10 ms 1.2 ms 150 s
A Logic [1] on bit D2 disables the overcurrent low (CD_dis) detection time-out feature. A Logic [1] on bit D3 disables the open load (OL) detection feature. Address x100 -- Direct Input Control Register (DICR) The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of the output. A Logic [0] on bit D1 will enable the output for direct control by the IN pin. A Logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the input was enabled for
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
direct control, a Logic [1] for the D0 bit will result in a Boolean AND of the IN pin with its corresponding D0 message bit when addressing the OCR register. Similarly, a Logic [0] on the D0 pin will result in a Boolean OR of the IN pin with the corresponding message bits when addressing the OCR register. The DICR register is useful if there is a need to independently turn on and off several loads that are PWM'd at the same frequency and duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN pins of several devices to a PWM output port from the MCU and configuring each of the outputs to be controlled via their respective direct IN pin. The DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output. A Logic [1] on bit D2 is used to select the high ratio (CSR1, 1/40000) on the CSNS pin. The default value [0] is used to select the low ratio (CSR0, 1/5400). A Logic [1] on bit D3 is used to select the high-speed slew rate. The default value [0] corresponds to the low speed slew rate. Address 0101 -- Output Switching Delay Register (OSDR) The OSDR register is used to configure the device with a programmable time delay that is active during Output On transitions that are initiated via SPI (not via direct input). Whenever the input is commanded to transition from Logic [0] to Logic [1], the output will be held OFF for the time delay configured in the OSDR register. The programming of the contents of this register has no effect on device Fail-Safe mode operation. The default value of the OSDR register is 000, equating to no delay, since the switching delay time is 0 ms. This feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be synchronously switched ON with a single command.
Table 13 shows the eight selectable output switching delay times, which range from 0 ms to 525 ms. Table 13. Switching Delay
OSD[2:0] (D2 : D0) Turn ON Delay (ms)
000 001 010 011 100 101 110 111
0 75 150 225 300 375 450 525
Address 1101 -- Watchdog Register (WDR) The WDR register is used by the MCU to configure the watchdog time-out. Watchdog time-out is configured using bits D1 and D0 (Table 14). When bits D1 and D0 are programmed for the desired watchdog time-out period, the WD bit (D7) should be toggled as well to ensure that the new time-out period is programmed at the beginning of a new count sequence. Table 14. Watchdog Time-out
WD [1:0] (D1: D0) Timing (ms)
00 01 10 11
620 310 2500 1250
Address 0110 -- No Action Register (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be affected by commands being clocked over a daisy-chained SPI configuration, and by toggling the WD bit (D7) the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Address 1110 -- Undervoltage / Overvoltage Register (UOVR) The UOVR register can be used to disable or enable the overvoltage and/or undervoltage protection. By default ([0]), both protections are active. When disabled, an undervoltage or overvoltage condition fault will not be reported in bits D1 and D0 of the output fault register. Address x111 -- TEST The TEST register is reserved for test and is not accessible with SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new message data is clocked into the SI pin. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant upon the previously written SPI word. Any bits clocked out of the SO pin after the first eight will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a Logic [0]. This feature is useful for daisy chaining devices as well as message verification. Table 15. Serial Output Bit Map Descriptions
Previous STATR D7, D2, D1, D0
A valid message length is determined following a CS transition of Logic [0] to Logic [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the STATR-selected register data at the time the CS is pulled to a Logic [0] during SPI communication and / or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. * The RST pin transition from a Logic [0] to Logic [1] while the WAKE pin is at Logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0 x x x x x 0 1 0 1 x 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1
OD7 WDin WDin WDin WDin WDin 0 1 0 1 WDin
OD6 OTF 0 0 0 1 1 1 1 1 -
OD5 OCHF 0 1 1 0 0 0 1 1 -
OD4 OCLF 1 0 1 0 1 1 0 0 -
OD3 OLF 0 SOCH OL_dis Fast SR FSM_HS 0 0 0 -
OD2 UVF 0 SOCL2 CD_dis CSNS high OSD2 WDTO IN Pin 0 -
OD1 OVF CSNS EN SOCL1 OCLT1 IN dis OSD1 WD1 FSI Pin UV_dis -
OD0 FAULT IN_SPI SOCL0 OCLT0 A/O OSD0 WD0 WAKE Pin OV_dis -
x = Don't care.
SERIAL OUTPUT BIT ASSIGNMENT
The eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 15 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The contents of bits OD6 : OD0 depend upon the bits D2 : D0 from the most recent STATR command SOA2 : SOA0.
Previous Address SOA[2:0] = 000 If the previous three MSBs are 000, bits OD6 : OD0 reflect the current state of the Fault register (FLTR) (Table 16). Previous Address SOA[2:0] = 001 The data in bits OD1 and OD0 contain CSNS EN and IN_SPI programmed bits, respectively.
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Previous Address SOA[2:0] = 010 The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 11), and the data in bits OD2, OD1, and OD0 contain the programmed overcurrent low detection levels (refer to Table 10). Table 16. Fault Register
OD7 x OD6 OTF OD5 OD4 OD3 OLF OD2 UVF OD1 OVF OD0 FAULT
Previous Address SOA[2:0] =100 The returned data contain the programmed values in the DICR. Previous Address SOA[2:0] =101 * SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS) reflects the state of the output in the Fail-Safe mode after a watchdog timeout occurs. * SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is Logic [1], the watchdog has timed out and the device is in Fail-Safe mode. If WDTO is Logic [0], the device is in Normal mode (assuming device is powered and not in the Sleep mode), with the watchdog either enabled or disabled. Previous Address SOA[2:0] =110 * SOA3 = 0. OD2, OD1, and OD0 return the state of the IN, FSI, and WAKE pins, respectively (Table 17). Table 17. Pin Register
OD2 OD1 OD0
OCHF OCLF
OD7 (x) = Don't care. OD6 (OTF) = Overtemperature Flag. OD5 (OCHF) = Overcurrent High Flag. (This fault is latched.) OD4 (OCLF) = Overcurrent Low Flag. (This fault is latched.) OD3 (OLF) = Open Load Flag. OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.) OD1 (OVF) = Overvoltage Flag. OD0 (FAULT) = This flag reports a fault and is reset by a read operation.
Note The FS pin reports a fault and is reset by a new Switch-ON command (via SPI or direct input IN).
IN Pin
FSI Pin
WAKE Pin
Previous Address SOA[2:0] = 011 The data returned in bits OD1 and OD0 are current values for the overcurrent fault blanking time, illustrated in Table 12. Bit OD2 reports when the overcurrent detection time-out feature is active. OD3 reports whether the open load circuitry is active.
* SOA3 = 1. The returned data contains the programmed values in the UOVR register. Bit OD1 reflects the state of the undervoltage protection, while bit OD0 reflects the state of the overvoltage protection (refer to Table 15). Previous Address SOA[2:0] = 111 Null Data. No previous register Read Back command received, so bits OD2, OD1, and OD0 are null, or 000.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
VPWR VDD Voltage Regulator VDD VDD NC VPWR VDD VPWR
10 k
10 k
10
MCU
100nF 10F
2
VDD NC WAKE IN SCLK CS RST SO SI FS CSNS FSI
33982B
VPWR
14
2.5F
12
10nF
I/O SCLK CS I/O SI SO I/O A/D
10k 10k 10k 10k 10k
4 8 7 3 11 9 5 1 6
NC HS
15
HS
16
LOAD GND
13
1k
RFS
Figure 11. Typical Applications
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PACKAGING SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
SOLDERING INFORMATION
The 33982B is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33982B was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:
* Convection: 225C +5 .0/ -0C * Vapor Phase Reflow (VPR): 215C to 219C * Infrared (IR) / Convection: 225C +5.0 / -0C The maximum peak temperature during the soldering process should not exceed 230C. The time at maximum temperature should range from 10 s to 40 s maximum.
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10596D.
PNA SUFFIX 16-PIN PQFN NONLEADED PACKAGE 98ARL10521D ISSUE C
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
PNA SUFFIX 16-PIN PQFN NONLEADED PACKAGE 98ARL10521D ISSUE C
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Introduction This thermal addendum is provided as a supplement to the MC33982B technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 RJA11 RJA12 RJA21 RJA22 P1 P2
33982
High-Side Switch
PNA SUFFIX 98ARL10521D 16-PIN PQFN 12 mm x 12 mm Note For package dimensions, refer to the 33982B data sheet.
=
.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 18. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2
1.0 0.2 1.0
RJAmn (1), (2) RJBmn
(2), (3)
20 6 53 <0.5
16 2.0 40 0.0
39 26 73
RJAmn (1), (4) RJCmn
(5)
0.2 1.0 * All measurements are in millimeters
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad.
Note: Recommended via diameter is 0.5 mm. PTH (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via.
Figure 12. Surface Mount for Power PQFN with Exposed Pads
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0)
Transparent Top View
A
WAKE CSNS RST
SCLK
VDD
FSI
12 11 10 9 8
Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air
NC
SO
CS
FS
IN
SI
7
65
4
3
2
1
13 GND
A
14 VPWR
15 HS
16 HS
33982B Pin Connections 16-Pin PQFN 0.90 mm Pitch 12.0 mm x 12.0 mm Body Figure 13. Thermal Test Board Table 19. Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Thermal Resistance Area A (mm2) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2
Outline:
0 RJAmn 300 600
55 41 39
42 32 29
74 66 65
Area A: Ambient Conditions:
RJA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 3.0)
80 Thermal Resistance [C/W] 70 60 50 40 30 20 10 0
x
RJA11 RJA22 RJA12 = RJA21
0
Heat spreading area A [mm]
300
600
Figure 14. Device on Thermal Test Board RJA
100
Thermal Resistance (CW)
10
1
x
0.1 1.00E-03
RJA11 RJA22 RJA12 = RJA21
1.00E+03 1.00E+04
1.00E-02
1.00E-01
1.00E+00
1.00E+01 Time(s)
1.00E+02
Figure 15. Transient Thermal Resistance RJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2)
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
10.0 11.0
2/2006 5/2006
* * * * * * * *
Implemented Revision History page Deletion of MC33982 part number, replaced with MC33982B. Corrected Pin Connections to the proper case outline Added final sentence to Open Load Fault (Non-Latching) Corrected heading labels on Input Timing Switching Characteristics Changed labels in the Typical Applications drawing Corrected Package Dimensions to Revision C Added Thermal Addendum (Rev 3.0).
12.0
1/2007
* Added RoHS logo to the data sheet
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MC33982 Rev. 12.0 1/2007

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